KURT PEDROSASIGNALS & SAWDUST

Channel 1 · Professional · FPGA / Digital Design / DSP

Datapaths,
delivered on time.

Digital design engineer specializing in FPGA logic and wideband DSP — parallel DDC/DUC chains at 16+ samples per clock, NCO/DDS engines, FSM-based timing control, AXI4/AXI-Stream infrastructure, and DMA pipelines into DDR4. Current platform: Zynq RFSoC. Primary domain: wideband receiver and signal-generation systems for aerospace & defense. Setup and hold both satisfied.

Résumé Projects Publications
DWG-000

Résumé

Summary

FPGA and digital design engineer with 10 years of professional experience. Currently implementing wideband DSP architectures on Zynq RFSoC at Aeronix — DDC/DUC chains, NCO/DDS engines at 16+ samples per clock, and a probability-of-detection receiver with spectral scanning and tracking of CW and pulse signals. Prior eight years at L3Harris Technologies leading FPGA design across EW, Space, and Avionics: Versal ACAP AI Engine integration, SpaceWire routing for space-grade systems, high-speed serial interfaces (10G Ethernet, Fiber Channel, PCIe), and management of a seven-engineer team. Fluent in VHDL from architecture sketch to lab-verified bitstream.

Revision history (experience — every engineer ships in revisions)

RevDescription of changeDate
REV E FPGA Engineer Aeronix
  • Implementing parallel DSP datapaths on Zynq RFSoC: DDC/DUC chains and NCO/DDS engines running 16+ samples per clock from a 312.5 MHz fabric clock.
  • Designing FSM-based timing and control logic for a probability-of-detection receiver with spectral scanning and CW/pulse signal tracking.
  • Building AXI4/AXI-Stream infrastructure and DMA/DDR4 data-movement pipelines; performing timing closure on dense RFSoC designs.
 2026 – Present
REV D Senior Supervisor — FPGA Engineer L3Harris Technologies · Palm Bay, FL
  • Engineer-in-charge of FPGA designs across EW, Space, and Avionics; performed timing closures using Xilinx and Microsemi tools per program requirements.
  • Led seven-engineer team: mid-year and end-of-year performance reviews, bi-weekly one-on-ones, and administrative oversight.
  • Implemented Digital Receiver on Xilinx Versal ACAP (VC1902) with AI Engines, PetaLinux, and PL; bit-true validated against MATLAB reference model in lab.
  • Designed 32-bit floating-point spectral tracker for signal classification and spectrum monitoring; results stored to 8 GB DDR4 via NoC.
  • Implemented 5-port SpaceWire router on Actel RTAX4000s (space-grade) with UART/Hamming interface to 24 Management Cards; NOR Flash controller with 4 LEON boot slots.
  • Designed Phased Array Antenna digital control: UDP/IP core, 10G Ethernet (PCS/PMA + MAC on GTX), and 5G sFPDP on Kintex-7.
 2017 – 2026
REV C Electronics Engineer Northrop Grumman · Melbourne, FL
  • Developed radar system simulator in MATLAB; performed simulations using MATLAB and proprietary tools.
  • Designed Python test scripts for Stores Management System software validation; executed formal software testing and integration.
 2015 – 2017
REV B M.S. Electrical Engineering Embry-Riddle Aeronautical University · Thesis: GPS signal generation on an SDR FPGA platform 2016
REV A B.S. Computer Engineering Embry-Riddle Aeronautical University 2015
INIT Naval Aircrewman — AWS/SAR United States Navy 2005 – 2012

Parts list (skills)

PN-001 LUT 95%FPGA DesignXilinx/AMD: Zynq RFSoC, Versal ACAP, UltraScale+, Kintex-7; Microsemi/Actel RTAX; Vivado, ISE, Libero; timing closure and floorplanning
PN-002 LUT 95%HDL — VHDL / SystemVerilogRTL from architecture to bitstream: packages, generics, self-checking testbenches
PN-003 DSP58 92%DSP DatapathsParallel 16+ SPC pipelines, DDC/DUC, NCO/DDS, FIR/polyphase, FFT, Prob-of-Detection receivers, AI Engine kernels
PN-004 LUT 88%Control LogicFSM design, precision timing (PRI/PW), CDC strategies, spectral scanning and CW/pulse tracking control
PN-005 BRAM 90%High-Speed InterfacesAXI4/AXI-Stream, SpaceWire, 10G Ethernet (PCS/PMA+MAC), Fiber Channel, PCIe Gen1, RS-485
PN-006 IO 85%Data MovementDMA, DDR4/DDR3 (MIG), NOR Flash, NoC (Versal), high-rate capture pipelines
PN-007 LUT 82%Simulation & VerificationCadence Incisive, Siemens Questa/CDC/RDC, Synopsys Synplify, MATLAB bit-true models
PN-008 —Languages & ToolsPython, Tcl, C/C++, Git, JIRA/Confluence, Sigasi; MATLAB/Octave for signal modeling

Download

Download PDF résumé

DWG-001+

Selected projects

DWG-001REV B

Digital receiver system

Wideband receiver on Xilinx Versal ACAP (VC1902) integrating AI Engines with Programmable Logic and PetaLinux. Implemented a 32-bit floating-point spectral tracker for signal classification; outputs stored to 8 GB DDR4 via NoC. Bit-true validated against MATLAB reference in lab.

Versal ACAPAI EnginesPetaLinuxSpectral Tracking
DWG-002REV A

Phased array antenna — digital control

Full digital control system for a phased-array antenna on Xilinx Kintex-7 (XC7K410T): custom UDP/IP core with 64-bit data bus, 10G Ethernet (PCS/PMA + MAC on GTX transceivers), 5G sFPDP interface, and MicroBlaze bare-metal DDR3 BIT. System-level simulation in Cadence SimVision.

Kintex-710G EthernetUDP/IPsFPDP
DWG-003REV A

GPS signal generator on ROACH SDR

Master's thesis: transformed the CASPER ROACH radio-astronomy processing board into a configurable GPS L1 C/A signal generator for receiver test and anti-spoofing research.

GPS/GNSSSDRCASPER
DWG-004REV A

Control & data handling — space

Lead designer on a radiation-tolerant C&DH system targeting Actel RTAX4000s. 5-port SpaceWire router for SBA bus traffic, UART/Hamming interface to 24 Management Cards, NOR Flash controller with 4 LEON boot slots and 8 GB payload storage.

SpaceWireRTAX4000sSpace-GradeLEON
DWG-005REV A

System time message emulator

Architected and implemented a 10 Hz time-message and strobe emulator on VCU118 (Virtex UltraScale+ XCVU9P): dual 10G Fiber Channel interfaces on GTY transceivers, PCIe Gen1 ×16 for host communication, RS-485 strobe output, and JTAG-to-AXI for in-lab debug.

UltraScale+10G FCPCIeRS-485
REF

Publications

Master's Thesis · Embry-Riddle Aeronautical University · Scholarly Commons · 2017

A GPS Signal Generator Using a ROACH FPGA Board

Kurt L. Pedrosa (advisor: W. C. Barott). Detailed design of a GPS L1 C/A signal generator built on the CASPER ROACH SDR processing board, enabling configurable signal manipulation for GPS receiver testing and anti-spoofing research.  Read on ERAU Scholarly Commons →

IEEE/ION PLANS 2016 Conference

Modular Two Antenna GNSS Signal Generator Based on SDR

Pedrosa, Kurt; Bojda, Petr. A modular dual-antenna GNSS signal generator architecture implemented on software-defined radio hardware.

2016 ASEE Southeast Section Conference

Fostering Agile Methodologies in Cross-Disciplinary Capstone Design Course through Process Management Tools

Pedrosa, Kurt; Tubbesing, Richard; Stansbury, Richard; Liu, Jianhua.

IEEE SoutheastCon 2016

A Design to Improve Selective Catalytic Reduction for Diesel Engines

Ye Sun, Anuj Sharma, Amay Desai, Kurt Pedrosa, Marc Compare, Ilteris Demirkiran.