St. Cloud, Florida · EST. one engineer, two channels

Two clock
domains. One engineer.

By day I design FPGA logic and DSP datapaths — pipelines, filters, and state machines that have to close timing. The rest of my cycles go to the wood shop, the jiu-jitsu mats, and three acres of chickens, gardens, and half-finished ideas. This site crosses between the two domains. Safely. With synchronizers.

SEL

Pick a channel

LOG

Recent entries